1. Technical Field
Embodiments relate to an integrated circuit provided with at least one integrated antenna. Embodiments particularly, but not exclusively, relate to an wafer integrated circuit and the following description is made with reference to this field of application by way of illustration only.
2. Discussion of the Related Art
As it is well known, for the electric selection of devices executed on wafer, i.e. the so called testing EWS (acronym from “Electrical-Wafer-Sorting”), it is necessary to electrically connect a tester or ATE (acronym from “Automated Test Equipment”) that executes measures on a wafer whereon there are electronic components to be tested or selected or probed, in particular integrated circuits or chips. A terminal portion of the test system is schematically shown in FIG. 1A, globally indicated with 1.
The interface between the real tester ATE 1A and a wafer 6 comprising a plurality of devices to be tested or selected, in particular chips 7 (also indicated as integrated circuits or IC, acronym from “Integrated Circuit”) is a so called probe card 2, which is essentially a board made of a PCB (acronym of “Printed Circuit Board”) and of a probe head 3 that comprises hundreds (many times thousands) of different probes 4 that electrically connect the tester ATE 1A to almost all the contact pads 8 of a chip 7 to be tested, as shown in greater detail but always schematically in FIG. 1B. In particular, each end portion or tip 9 of the probes 4 enters in contact with a contact pad 8 of the chip 7.
In general, the wafer 6 groups a plurality of chips 7 to be tested, and during the testing steps it is placed on a support called chuck 5, shown in the portion of the test system 1, and belonging to an apparatus called also prober (not shown in the figure), this support being thus indicated also as prober chuck.
The number of contact pads 8 being needed for a determined testing may be smaller or identical to the total number of contact pads 8 present on the chip 7 to be tested.
The procedure goes on in a similar way even if on the chips 7 there are contact bumps instead of contact pads 8, as it is well known to technicians in the field.
For positioning the probes 4 on the contact pads 8, the prober uses optical recognition operated by video cameras which focus on some details on one side of the wafer and on the other the probes or special bidimensional markers called Fiducials (not shown) which are placed on the probe card 2 outside the array of probes 4. However, the recognition of these bidimensional Fiducials requires additional algorithms and necessitates ties on the construction of the probe card 2, and in particular on the realization of the array of probes 4.
Before each chip 7 is encapsulated into a respective package, it is known that it is necessary to execute the testing of the chip 7 itself still on the wafer 6, by using the probes 4 that are directly connected to the contact pads 8, and that thus execute the so called probing of the contact pad 8 they enter in contact with.
After the testing, the wafer 6 is cut and the chips 7 that have been tested and proved to be working are assembled in their package, ready for further process steps, also comprising final testing steps of the chip 7 themselves in the package wherein they have been assembled.
To this purpose, on the wafer 6, between a chip 7 and another, an area is created called scribe line SL within which a saw or a laser will pass during the cutting or singulation operation, necessary for separating the various devices present on the wafer for executing the various assembling and encapsulating or packaging steps of the same devices, as schematically shown in FIG. 2. In particular, in the schematic enlargement indicated by way of illustration in FIG. 2, a group of four chips 7, indicated as IC A, IC B, IC C and IC D, is separated by a first scribe line SL1, in particular horizontal according to the local reference of the figure, and a second scribe line SL2, in particular vertical, in the local reference of the figure.
Moreover, as shown in this figure, in the scribe lines (in particular in the first scribe line SL1) elementary structures are introduced, usually indicated as structures TEG (acronym of “Test Element Group”), these structures being used, for example, for the testing of some process parameters, which are measured in general before the electric test on wafer EWS.
Further, each chip 7 is surrounded, in a known way to those skilled in the art, by a protection structure, the so called seal ring 7A.
More in particular, the seal ring 7A has the aim of sealing the respective chip 7 and strengthening it mechanically for ensuring its reliability also further to the mechanical effort exerted by the saw during the cut or singulation of the chip 7 from the wafer 6.
The seal ring 7A is usually placed between an area where the contact pads of the chip itself, normally indicated as pad ring, and the scribe line SL confining with the chip itself are placed.
It is known that the seal ring 7A comprises a plurality of metal layers and of vias that connect them so as to realize a structure able to also block ions and polluting substances (such as, for example, humidity) which could jeopardize the proper operation of the chip 7 after the singulation.
Different implementations are known for the realization of a seal ring of an integrated electronic device or chip. For example, in U.S. Pat. No. 6,300,223 by Chang et al., there is described a structure of a seal ring where dielectric layers and metallic layers are alternated, the structure being also provided with a trench for reducing the mechanical stresses at the singulation of the chips from the wafer. Other structures suitable for realizing a seal ring are also known from U.S. Pat. No. 7,605,448 by Furusawa et al. and U.S. Pat. No. 6,492,716 by Bothra et al.
For avoiding problems of radiofrequency interferences that could jeopardize the operation of the chip, it is also known to suitably cut the seal ring in those points where substrate disturbances could be injected, these disturbances coming from internal circuits of the chip itself (such as power amplifiers, clock signal generators, input/output digital signal processing circuits, etc).
This technique for cutting the seal ring is also diffusely adopted for problems tied to the coupling with integrated inducers used at radiofrequency and microwaves for the following circuits: LNA, mixer, VCO, filters, etc. This measure is adopted in this case with the aim of eliminating the currents induced in the seal ring further to the passage of current in the inducers themselves, in particular the so called “eddy currents” or Foucault currents. In substance, the seal ring is cut so as to have an open ring structure, instead of a closed ring one, so as to avoid that it comprises coils through which the eddy currents could flow.
This technique for cutting the seal ring is also adopted for problems tied to the coupling with typically inductive integrated antennas used at radiofrequency and microwaves for the transmission of wireless signals. This measure is also, in this case, adopted so as to eliminate the currents induced in the seal ring further to the passage of current in the antennas themselves. Like in the previous case, the seal ring is cut so as to have an open ring structure, instead of closed ring, so as to avoid that circular paths are formed through which the eddy currents could flow.
It is to be specified that the eddy currents are such as to oppose against the currents generated in the antennas and/or in the inducers as provided by the law of Faraday-Lenz. The drawback of these currents is thus that they produce a magnetic flow that opposes against the variation of magnetic flow produced by the antenna and/or by the inducer present in the chip with a consequent reduction of its efficiency, in particular the negative mutual coupling of the currents reduces the value of the effective inductance, while the energy dissipated by the eddy currents reduces the quality factor Q, as it is evident from the following relation (referred to an inducer under optimal conditions):
  Q  ≅            ω      ·      Ls        Rs  
being:
ω is the pulse of the current sinusoid that flows through the antenna and/or the inducer;
Ls the inductance value of the antenna and/or of the inducer; and
Rs the resistance value of the antenna and/or of the inducer.
It is also well known that a generic electronic device or chip is connected to the surrounding world through connections such as wired channels (for example, cables, optical fibers, . . . ) or wireless channels (for example of the electromagnetic type). These connections allow for the exchange of information signals and/or to supply the chips themselves.
In case signals are to be exchanged through transmission of the magnetic or electromagnetic type between a chip and at least another external system, the chip should have inside at least one receiver/transmitter, also indicated as transceiver/transponder, connected to at least one antenna that may be incorporated in the chip itself, as schematically shown in FIG. 3.
In particular, the chip 10 comprises a plurality of circuit portions 11, indicated also as Core 1 . . . Core 4, at least one of which, in particular Core 1, connected to an antenna 12 through a device transmitter/receiver or transceiver/transponder 13.
Examples of chips provided with an antenna are the circuits RFId (acronym of “Radio Frequency Identification”) or the Smart Cards, that are low power integrated circuits (low power IC), that may be supplied and exchange information through the wireless channels (and thus without contact or contactless) that use transmission of the magnetic and/or electromagnetic type obtained by means of at least two antennas, of the type shown schematically in FIGS. 4A and 4B.
The RFId circuit, globally indicated in these figures with 15, comprises an antenna 17A, that may be, for example, a magnetic dipole or a hertzian dipole, which is connected to a chip 16A (in particular a RFId/Smart Card IC) in general by using bumps or wire bonds. The antenna 17A and the chip 16A are, in general, both contained in a single package. The antenna 17A is connected to the chip 16A, and this antenna 17A may be outside the chip 16A, as indicated in FIG. 4A, or it may be embedded, and thus be part of an overall integrated circuit 16B a portion of which is the chip 16A, as indicated in FIG. 4B.
The RFId circuit 15 communicates, by means of the exchange of electromagnetic waves 18, with an external system, for example a reader 14 that comprises in turn an antenna 17B and a reading system (RFId/Smart Card Reader) 19, including at least one chip 16C with characteristics functionally compatible with respect to the chip 16A.
The antenna 17A of FIG. 4B of the RFId circuit 15 may be of the magnetic type, in particular of the near field inductive type, and may be positioned around the chip 16A, with an increase of the area of the overall integrated circuit 16B itself and a consequent reduction of the total number of RFId circuits that may be placed on a wafer.
Antennas that work by using the electromagnetic field are described, for example, in published US patent application No. US 2010/0026601 in the name of Chang et al. In particular, these antennas are used for cell phones and operate far field thanks exactly to the electromagnetic field, comprising structures similar to hertzian dipoles or monopoles, suitably provided with reflectors. The structures proposed should not have metallic parts positioned above the antenna, which might screen the electromagnetic field. Also in this case, the antennas occupy a large area, with consequent increase in the area of the integrated circuit that comprises them.
Alternatively, the antenna may be also integrated above the chip to avoid such an area increase obtaining an On-Chip Antenna (OCA).
In this case, the performance of the antenna of the embedded type is however to be optimized, for maximizing the transfer of power, the electromagnetic energy exchanged being used also for supplying the chip that comprises the embedded antenna.
In particular, a known process for creating an antenna of the integrated or embedded type is a traditional diffusion process, which requires, however, additional masks and additional steps with respect to the wafer manufacturing process. Post processing methodologies are also known to create lower cost embedded antennas.
In each case, the antennas of the embedded type, now very used for RFId or Smart Cards, have a limited operational range due to their sizes.
Antennas of the capacitive type are also known, that use the generic pad of a chip as an armature of a capacitor.
In substance, the known solutions for realizing antennas integrated in a chip should use suitable structures, having reduced sizes when they are dedicated to the sole exchange of signals.
When instead also the power is to be transferred through the antenna, it is necessary to integrate with it structures of greater sizes. These structures, however, may have the following drawbacks and/or constraints:                if placed on the chip, they may require the use of integration processes that involve at least one further metallization level with respect to the realization of the chip itself, and        if placed around the chip, they may increase its area.        
These drawbacks and/or constraints linked to the integration of antennas in a chip may require, in each case, an increase of the relative manufacturing cost.
Moreover, the presence of structures such as, for example, the seal ring is however suitable for avoiding damages also of the integrated antennas during the cutting step of the wafer, i.e. of singulation of the chips realized therein.